`include "soc_config.v"
module Rena(
  input        clk  ,
  input        rst_n,
  // JTAG
  input       jtag_TCK,
  input       jtag_TMS,
  input       jtag_TDI,
  output      jtag_TDO,
  // UART
  input        uart_rx,
  output       uart_tx,
  // SPI
  output       spi_clk  ,
  output       spi_csn0 ,
  output       spi_csn1 ,
  output       spi_csn2 ,
  output       spi_csn3 ,
  output       spi_sdo0 ,
  output       spi_sdo1 ,
  output       spi_sdo2 ,
  output       spi_sdo3 ,
  output       spi_oe0  ,
  output       spi_oe1  ,
  output       spi_oe2  ,
  output       spi_oe3  ,
  input        spi_sdi0 ,
  input        spi_sdi1 ,
  input        spi_sdi2 ,
  input        spi_sdi3 ,
  inout [15:0] gpio
);
wire  plic_int = 0;
wire                             cpu_ar_ready  ;
wire                             cpu_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      cpu_ar_addr   ;
wire  [2:0]                      cpu_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        cpu_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      cpu_ar_user   ;
wire  [7:0]                      cpu_ar_len    ;
wire  [2:0]                      cpu_ar_size   ;
wire  [1:0]                      cpu_ar_burst  ;
wire                             cpu_ar_lock   ;
wire  [3:0]                      cpu_ar_cache  ;
wire  [3:0]                      cpu_ar_qos    ;
wire                             cpu_r_ready  ;
wire                             cpu_r_valid  ;
wire [1:0]                       cpu_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       cpu_r_data   ;
wire                             cpu_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         cpu_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       cpu_r_user   ;
wire                             cpu_aw_ready ;    
wire                             cpu_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      cpu_aw_addr  ;
wire  [2:0]                      cpu_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        cpu_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      cpu_aw_user  ;  
wire  [7:0]                      cpu_aw_len   ;   
wire  [2:0]                      cpu_aw_size  ;
wire  [1:0]                      cpu_aw_burst ;
wire                             cpu_aw_lock  ;
wire  [3:0]                      cpu_aw_cache ;
wire  [3:0]                      cpu_aw_qos   ;
wire                             cpu_w_ready  ;
wire                             cpu_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      cpu_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    cpu_w_strb   ;
wire                             cpu_w_last   ;
wire  [`AXI_USER_WIDTH-1:0]      cpu_w_user   ;
wire                             cpu_b_ready  ;
wire                             cpu_b_valid  ;
wire  [1:0]                      cpu_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        cpu_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      cpu_b_user   ;

wire  [`AXI_USER_WIDTH-1:0]      npu_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      debug_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      timer_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      plic_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      uart_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      gpio_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      spi_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      debugcfg_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      bootrom_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      npucfg_w_user   ;
wire  [`AXI_USER_WIDTH-1:0]      ddr_w_user   ;

wire                             npu_ar_ready  ;
wire                             npu_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      npu_ar_addr   ;
wire  [2:0]                      npu_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        npu_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      npu_ar_user   ;
wire  [7:0]                      npu_ar_len    ;
wire  [2:0]                      npu_ar_size   ;
wire  [1:0]                      npu_ar_burst  ;
wire                             npu_ar_lock   ;
wire  [3:0]                      npu_ar_cache  ;
wire  [3:0]                      npu_ar_qos    ;
wire                             npu_r_ready  ;
wire                             npu_r_valid  ;
wire [1:0]                       npu_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       npu_r_data   ;
wire                             npu_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         npu_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       npu_r_user   ;
wire                             npu_aw_ready ;    
wire                             npu_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      npu_aw_addr  ;
wire  [2:0]                      npu_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        npu_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      npu_aw_user  ;  
wire  [7:0]                      npu_aw_len   ;   
wire  [2:0]                      npu_aw_size  ;
wire  [1:0]                      npu_aw_burst ;
wire                             npu_aw_lock  ;
wire  [3:0]                      npu_aw_cache ;
wire  [3:0]                      npu_aw_qos   ;
wire                             npu_w_ready  ;
wire                             npu_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      npu_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    npu_w_strb   ;
wire                             npu_w_last   ;
wire                             npu_b_ready  ;
wire                             npu_b_valid  ;
wire  [1:0]                      npu_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        npu_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      npu_b_user   ;

wire                             debug_ar_ready  ;
wire                             debug_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      debug_ar_addr   ;
wire  [2:0]                      debug_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        debug_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      debug_ar_user   ;
wire  [7:0]                      debug_ar_len    ;
wire  [2:0]                      debug_ar_size   ;
wire  [1:0]                      debug_ar_burst  ;
wire                             debug_ar_lock   ;
wire  [3:0]                      debug_ar_cache  ;
wire  [3:0]                      debug_ar_qos    ;
wire                             debug_r_ready  ;
wire                             debug_r_valid  ;
wire [1:0]                       debug_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       debug_r_data   ;
wire                             debug_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         debug_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       debug_r_user   ;
wire                             debug_aw_ready ;    
wire                             debug_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      debug_aw_addr  ;
wire  [2:0]                      debug_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        debug_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      debug_aw_user  ;  
wire  [7:0]                      debug_aw_len   ;   
wire  [2:0]                      debug_aw_size  ;
wire  [1:0]                      debug_aw_burst ;
wire                             debug_aw_lock  ;
wire  [3:0]                      debug_aw_cache ;
wire  [3:0]                      debug_aw_qos   ;
wire                             debug_w_ready  ;
wire                             debug_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      debug_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    debug_w_strb   ;
wire                             debug_w_last   ;
wire                             debug_b_ready  ;
wire                             debug_b_valid  ;
wire  [1:0]                      debug_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        debug_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      debug_b_user   ;

wire                             timer_ar_ready  ;
wire                             timer_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      timer_ar_addr   ;
wire  [2:0]                      timer_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        timer_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      timer_ar_user   ;
wire  [7:0]                      timer_ar_len    ;
wire  [2:0]                      timer_ar_size   ;
wire  [1:0]                      timer_ar_burst  ;
wire                             timer_ar_lock   ;
wire  [3:0]                      timer_ar_cache  ;
wire  [3:0]                      timer_ar_qos    ;
wire                             timer_r_ready  ;
wire                             timer_r_valid  ;
wire [1:0]                       timer_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       timer_r_data   ;
wire                             timer_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         timer_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       timer_r_user   ;
wire                             timer_aw_ready ;    
wire                             timer_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      timer_aw_addr  ;
wire  [2:0]                      timer_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        timer_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      timer_aw_user  ;  
wire  [7:0]                      timer_aw_len   ;   
wire  [2:0]                      timer_aw_size  ;
wire  [1:0]                      timer_aw_burst ;
wire                             timer_aw_lock  ;
wire  [3:0]                      timer_aw_cache ;
wire  [3:0]                      timer_aw_qos   ;
wire                             timer_w_ready  ;
wire                             timer_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      timer_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    timer_w_strb   ;
wire                             timer_w_last   ;
wire                             timer_b_ready  ;
wire                             timer_b_valid  ;
wire  [1:0]                      timer_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        timer_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      timer_b_user   ;

wire                             plic_ar_ready  ;
wire                             plic_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      plic_ar_addr   ;
wire  [2:0]                      plic_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        plic_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      plic_ar_user   ;
wire  [7:0]                      plic_ar_len    ;
wire  [2:0]                      plic_ar_size   ;
wire  [1:0]                      plic_ar_burst  ;
wire                             plic_ar_lock   ;
wire  [3:0]                      plic_ar_cache  ;
wire  [3:0]                      plic_ar_qos    ;
wire                             plic_r_ready  ;
wire                             plic_r_valid  ;
wire [1:0]                       plic_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       plic_r_data   ;
wire                             plic_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         plic_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       plic_r_user   ;
wire                             plic_aw_ready ;    
wire                             plic_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      plic_aw_addr  ;
wire  [2:0]                      plic_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        plic_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      plic_aw_user  ;  
wire  [7:0]                      plic_aw_len   ;   
wire  [2:0]                      plic_aw_size  ;
wire  [1:0]                      plic_aw_burst ;
wire                             plic_aw_lock  ;
wire  [3:0]                      plic_aw_cache ;
wire  [3:0]                      plic_aw_qos   ;
wire                             plic_w_ready  ;
wire                             plic_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      plic_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    plic_w_strb   ;
wire                             plic_w_last   ;
wire                             plic_b_ready  ;
wire                             plic_b_valid  ;
wire  [1:0]                      plic_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        plic_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      plic_b_user   ;

wire                             uart_ar_ready  ;
wire                             uart_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      uart_ar_addr   ;
wire  [2:0]                      uart_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        uart_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      uart_ar_user   ;
wire  [7:0]                      uart_ar_len    ;
wire  [2:0]                      uart_ar_size   ;
wire  [1:0]                      uart_ar_burst  ;
wire                             uart_ar_lock   ;
wire  [3:0]                      uart_ar_cache  ;
wire  [3:0]                      uart_ar_qos    ;
wire                             uart_r_ready  ;
wire                             uart_r_valid  ;
wire [1:0]                       uart_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       uart_r_data   ;
wire                             uart_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         uart_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       uart_r_user   ;
wire                             uart_aw_ready ;    
wire                             uart_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      uart_aw_addr  ;
wire  [2:0]                      uart_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        uart_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      uart_aw_user  ;  
wire  [7:0]                      uart_aw_len   ;   
wire  [2:0]                      uart_aw_size  ;
wire  [1:0]                      uart_aw_burst ;
wire                             uart_aw_lock  ;
wire  [3:0]                      uart_aw_cache ;
wire  [3:0]                      uart_aw_qos   ;
wire                             uart_w_ready  ;
wire                             uart_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      uart_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    uart_w_strb   ;
wire                             uart_w_last   ;
wire                             uart_b_ready  ;
wire                             uart_b_valid  ;
wire  [1:0]                      uart_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        uart_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      uart_b_user   ;

wire                             gpio_ar_ready  ;
wire                             gpio_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      gpio_ar_addr   ;
wire  [2:0]                      gpio_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        gpio_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      gpio_ar_user   ;
wire  [7:0]                      gpio_ar_len    ;
wire  [2:0]                      gpio_ar_size   ;
wire  [1:0]                      gpio_ar_burst  ;
wire                             gpio_ar_lock   ;
wire  [3:0]                      gpio_ar_cache  ;
wire  [3:0]                      gpio_ar_qos    ;
wire                             gpio_r_ready  ;
wire                             gpio_r_valid  ;
wire [1:0]                       gpio_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       gpio_r_data   ;
wire                             gpio_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         gpio_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       gpio_r_user   ;
wire                             gpio_aw_ready ;    
wire                             gpio_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      gpio_aw_addr  ;
wire  [2:0]                      gpio_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        gpio_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      gpio_aw_user  ;  
wire  [7:0]                      gpio_aw_len   ;   
wire  [2:0]                      gpio_aw_size  ;
wire  [1:0]                      gpio_aw_burst ;
wire                             gpio_aw_lock  ;
wire  [3:0]                      gpio_aw_cache ;
wire  [3:0]                      gpio_aw_qos   ;
wire                             gpio_w_ready  ;
wire                             gpio_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      gpio_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    gpio_w_strb   ;
wire                             gpio_w_last   ;
wire                             gpio_b_ready  ;
wire                             gpio_b_valid  ;
wire  [1:0]                      gpio_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        gpio_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      gpio_b_user   ;

wire                             spi_ar_ready  ;
wire                             spi_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      spi_ar_addr   ;
wire  [2:0]                      spi_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        spi_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      spi_ar_user   ;
wire  [7:0]                      spi_ar_len    ;
wire  [2:0]                      spi_ar_size   ;
wire  [1:0]                      spi_ar_burst  ;
wire                             spi_ar_lock   ;
wire  [3:0]                      spi_ar_cache  ;
wire  [3:0]                      spi_ar_qos    ;
wire                             spi_r_ready  ;
wire                             spi_r_valid  ;
wire [1:0]                       spi_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       spi_r_data   ;
wire                             spi_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         spi_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       spi_r_user   ;
wire                             spi_aw_ready ;    
wire                             spi_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      spi_aw_addr  ;
wire  [2:0]                      spi_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        spi_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      spi_aw_user  ;  
wire  [7:0]                      spi_aw_len   ;   
wire  [2:0]                      spi_aw_size  ;
wire  [1:0]                      spi_aw_burst ;
wire                             spi_aw_lock  ;
wire  [3:0]                      spi_aw_cache ;
wire  [3:0]                      spi_aw_qos   ;
wire                             spi_w_ready  ;
wire                             spi_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      spi_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    spi_w_strb   ;
wire                             spi_w_last   ;
wire                             spi_b_ready  ;
wire                             spi_b_valid  ;
wire  [1:0]                      spi_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        spi_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      spi_b_user   ;

wire                             debugcfg_ar_ready  ;
wire                             debugcfg_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      debugcfg_ar_addr   ;
wire  [2:0]                      debugcfg_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        debugcfg_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      debugcfg_ar_user   ;
wire  [7:0]                      debugcfg_ar_len    ;
wire  [2:0]                      debugcfg_ar_size   ;
wire  [1:0]                      debugcfg_ar_burst  ;
wire                             debugcfg_ar_lock   ;
wire  [3:0]                      debugcfg_ar_cache  ;
wire  [3:0]                      debugcfg_ar_qos    ;
wire                             debugcfg_r_ready  ;
wire                             debugcfg_r_valid  ;
wire [1:0]                       debugcfg_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       debugcfg_r_data   ;
wire                             debugcfg_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         debugcfg_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       debugcfg_r_user   ;
wire                             debugcfg_aw_ready ;    
wire                             debugcfg_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      debugcfg_aw_addr  ;
wire  [2:0]                      debugcfg_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        debugcfg_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      debugcfg_aw_user  ;  
wire  [7:0]                      debugcfg_aw_len   ;   
wire  [2:0]                      debugcfg_aw_size  ;
wire  [1:0]                      debugcfg_aw_burst ;
wire                             debugcfg_aw_lock  ;
wire  [3:0]                      debugcfg_aw_cache ;
wire  [3:0]                      debugcfg_aw_qos   ;
wire                             debugcfg_w_ready  ;
wire                             debugcfg_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      debugcfg_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    debugcfg_w_strb   ;
wire                             debugcfg_w_last   ;
wire                             debugcfg_b_ready  ;
wire                             debugcfg_b_valid  ;
wire  [1:0]                      debugcfg_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        debugcfg_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      debugcfg_b_user   ;

wire                             bootrom_ar_ready  ;
wire                             bootrom_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      bootrom_ar_addr   ;
wire  [2:0]                      bootrom_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        bootrom_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      bootrom_ar_user   ;
wire  [7:0]                      bootrom_ar_len    ;
wire  [2:0]                      bootrom_ar_size   ;
wire  [1:0]                      bootrom_ar_burst  ;
wire                             bootrom_ar_lock   ;
wire  [3:0]                      bootrom_ar_cache  ;
wire  [3:0]                      bootrom_ar_qos    ;
wire                             bootrom_r_ready  ;
wire                             bootrom_r_valid  ;
wire [1:0]                       bootrom_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       bootrom_r_data   ;
wire                             bootrom_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         bootrom_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       bootrom_r_user   ;
wire                             bootrom_aw_ready ;    
wire                             bootrom_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      bootrom_aw_addr  ;
wire  [2:0]                      bootrom_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        bootrom_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      bootrom_aw_user  ;  
wire  [7:0]                      bootrom_aw_len   ;   
wire  [2:0]                      bootrom_aw_size  ;
wire  [1:0]                      bootrom_aw_burst ;
wire                             bootrom_aw_lock  ;
wire  [3:0]                      bootrom_aw_cache ;
wire  [3:0]                      bootrom_aw_qos   ;
wire                             bootrom_w_ready  ;
wire                             bootrom_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      bootrom_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    bootrom_w_strb   ;
wire                             bootrom_w_last   ;
wire                             bootrom_b_ready  ;
wire                             bootrom_b_valid  ;
wire  [1:0]                      bootrom_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        bootrom_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      bootrom_b_user   ;

wire                             npucfg_ar_ready  ;
wire                             npucfg_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      npucfg_ar_addr   ;
wire  [2:0]                      npucfg_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        npucfg_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      npucfg_ar_user   ;
wire  [7:0]                      npucfg_ar_len    ;
wire  [2:0]                      npucfg_ar_size   ;
wire  [1:0]                      npucfg_ar_burst  ;
wire                             npucfg_ar_lock   ;
wire  [3:0]                      npucfg_ar_cache  ;
wire  [3:0]                      npucfg_ar_qos    ;
wire                             npucfg_r_ready  ;
wire                             npucfg_r_valid  ;
wire [1:0]                       npucfg_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       npucfg_r_data   ;
wire                             npucfg_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         npucfg_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       npucfg_r_user   ;
wire                             npucfg_aw_ready ;    
wire                             npucfg_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      npucfg_aw_addr  ;
wire  [2:0]                      npucfg_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        npucfg_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      npucfg_aw_user  ;  
wire  [7:0]                      npucfg_aw_len   ;   
wire  [2:0]                      npucfg_aw_size  ;
wire  [1:0]                      npucfg_aw_burst ;
wire                             npucfg_aw_lock  ;
wire  [3:0]                      npucfg_aw_cache ;
wire  [3:0]                      npucfg_aw_qos   ;
wire                             npucfg_w_ready  ;
wire                             npucfg_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      npucfg_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    npucfg_w_strb   ;
wire                             npucfg_w_last   ;
wire                             npucfg_b_ready  ;
wire                             npucfg_b_valid  ;
wire  [1:0]                      npucfg_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        npucfg_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      npucfg_b_user   ;

wire                             ddr_ar_ready  ;
wire                             ddr_ar_valid  ;
wire  [`AXI_ADDR_WIDTH-1:0]      ddr_ar_addr   ;
wire  [2:0]                      ddr_ar_prot   ;
wire  [`AXI_ID_WIDTH-1:0]        ddr_ar_id     ;
wire  [`AXI_USER_WIDTH-1:0]      ddr_ar_user   ;
wire  [7:0]                      ddr_ar_len    ;
wire  [2:0]                      ddr_ar_size   ;
wire  [1:0]                      ddr_ar_burst  ;
wire                             ddr_ar_lock   ;
wire  [3:0]                      ddr_ar_cache  ;
wire  [3:0]                      ddr_ar_qos    ;
wire                             ddr_r_ready  ;
wire                             ddr_r_valid  ;
wire [1:0]                       ddr_r_resp   ;
wire [`AXI_DATA_WIDTH-1:0]       ddr_r_data   ;
wire                             ddr_r_last   ;
wire [`AXI_ID_WIDTH-1:0]         ddr_r_id     ;
wire [`AXI_USER_WIDTH-1:0]       ddr_r_user   ;
wire                             ddr_aw_ready ;    
wire                             ddr_aw_valid ;
wire  [`AXI_ADDR_WIDTH-1:0]      ddr_aw_addr  ;
wire  [2:0]                      ddr_aw_prot  ;
wire  [`AXI_ID_WIDTH-1:0]        ddr_aw_id    ;
wire  [`AXI_USER_WIDTH-1:0]      ddr_aw_user  ;  
wire  [7:0]                      ddr_aw_len   ;   
wire  [2:0]                      ddr_aw_size  ;
wire  [1:0]                      ddr_aw_burst ;
wire                             ddr_aw_lock  ;
wire  [3:0]                      ddr_aw_cache ;
wire  [3:0]                      ddr_aw_qos   ;
wire                             ddr_w_ready  ;
wire                             ddr_w_valid  ;
wire  [`AXI_DATA_WIDTH-1:0]      ddr_w_data   ;
wire  [`AXI_DATA_WIDTH/8-1:0]    ddr_w_strb   ;
wire                             ddr_w_last   ;
wire                             ddr_b_ready  ;
wire                             ddr_b_valid  ;
wire  [1:0]                      ddr_b_resp   ;
wire  [`AXI_ID_WIDTH-1:0]        ddr_b_id     ;
wire  [`AXI_USER_WIDTH-1:0]      ddr_b_user   ;
wire [15:0] gpio_i  ;
wire [15:0] gpio_o  ;
wire [15:0] gpio_oe ;

assign gpio_i = gpio;
assign gpio[0 ]   = gpio_oe[0 ] ? gpio_o[0 ] : 1'bz;
assign gpio[1 ]   = gpio_oe[1 ] ? gpio_o[1 ] : 1'bz;
assign gpio[2 ]   = gpio_oe[2 ] ? gpio_o[2 ] : 1'bz;
assign gpio[3 ]   = gpio_oe[3 ] ? gpio_o[3 ] : 1'bz;
assign gpio[4 ]   = gpio_oe[4 ] ? gpio_o[4 ] : 1'bz;
assign gpio[5 ]   = gpio_oe[5 ] ? gpio_o[5 ] : 1'bz;
assign gpio[6 ]   = gpio_oe[6 ] ? gpio_o[6 ] : 1'bz;
assign gpio[7 ]   = gpio_oe[7 ] ? gpio_o[7 ] : 1'bz;
assign gpio[8 ]   = gpio_oe[8 ] ? gpio_o[8 ] : 1'bz;
assign gpio[9 ]   = gpio_oe[9 ] ? gpio_o[9 ] : 1'bz;
assign gpio[10]   = gpio_oe[10] ? gpio_o[10] : 1'bz;
assign gpio[11]   = gpio_oe[11] ? gpio_o[11] : 1'bz;
assign gpio[12]   = gpio_oe[12] ? gpio_o[12] : 1'bz;
assign gpio[13]   = gpio_oe[13] ? gpio_o[13] : 1'bz;
assign gpio[14]   = gpio_oe[14] ? gpio_o[14] : 1'bz;
assign gpio[15]   = gpio_oe[15] ? gpio_o[15] : 1'bz;


CPU CPU(
  .clk  (clk  ),
  .rst_n(rst_n),
  // 用户定义的可屏蔽中断 不影响核心运行的中断
  .user_interrupt(plic_int),
  // 不可屏蔽的关键中断 例如 UPS断电信号 核心外设错误信号
  .sys_interrupt(1'b0),
  /* AXI Master */
  .boot_addr(`START_ADDR),
  /* AR  */
  .axi_ar_ready (cpu_ar_ready ) ,
  .axi_ar_valid (cpu_ar_valid ) ,
  .axi_ar_addr  (cpu_ar_addr  ) ,
  .axi_ar_prot  (cpu_ar_prot  ) ,
  .axi_ar_id    (cpu_ar_id    ) ,
  .axi_ar_user  (cpu_ar_user  ) ,
  .axi_ar_len   (cpu_ar_len   ) ,
  .axi_ar_size  (cpu_ar_size  ) ,
  .axi_ar_burst (cpu_ar_burst ) ,
  .axi_ar_lock  (cpu_ar_lock  ) ,
  .axi_ar_cache (cpu_ar_cache ) ,
  .axi_ar_qos   (cpu_ar_qos   ) ,
  /* R */
  .axi_r_ready   (cpu_r_ready ),
  .axi_r_valid   (cpu_r_valid ),
  .axi_r_resp    (cpu_r_resp  ),
  .axi_r_data    (cpu_r_data  ),
  .axi_r_last    (cpu_r_last  ),
  .axi_r_id      (cpu_r_id    ),
  .axi_r_user    (cpu_r_user  ),
  /* AW */
  .axi_aw_ready (cpu_aw_ready ) ,       
  .axi_aw_valid (cpu_aw_valid ) ,   
  .axi_aw_addr  (cpu_aw_addr  ) ,   
  .axi_aw_prot  (cpu_aw_prot  ) ,   
  .axi_aw_id    (cpu_aw_id    ) ,
  .axi_aw_user  (cpu_aw_user  ) ,     
  .axi_aw_len   (cpu_aw_len   ) ,      
  .axi_aw_size  (cpu_aw_size  ) ,
  .axi_aw_burst (cpu_aw_burst ) ,
  .axi_aw_lock  (cpu_aw_lock  ) ,   
  .axi_aw_cache (cpu_aw_cache ) ,   
  .axi_aw_qos   (cpu_aw_qos   ) ,   
  /* W */
  .axi_w_ready  (cpu_w_ready   ) ,  
  .axi_w_valid  (cpu_w_valid   ) ,
  .axi_w_data   (cpu_w_data    ) ,   
  .axi_w_strb   (cpu_w_strb    ) ,   
  .axi_w_last   (cpu_w_last    ) ,   
  /* B */
  .axi_b_ready  (cpu_b_ready ) ,
  .axi_b_valid  (cpu_b_valid ) ,
  .axi_b_resp   (cpu_b_resp  ) ,  
  .axi_b_id     (cpu_b_id    ) ,
  .axi_b_user   (cpu_b_user  )   
);

npu_dummy #(
  .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
  .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
  .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
  .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)NPU(
    .clk   (clk  ),
    .rst_n (rst_n),
    .cfg_axi_arready (npucfg_ar_ready ), 
    .cfg_axi_arvalid (npucfg_ar_valid ), 
    .cfg_axi_araddr  (npucfg_ar_addr  ), 
    .cfg_axi_arprot  (npucfg_ar_prot  ), 
    .cfg_axi_arid    (npucfg_ar_id    ), 
    .cfg_axi_aruser  (npucfg_ar_user  ), 
    .cfg_axi_arlen   (npucfg_ar_len   ), 
    .cfg_axi_arsize  (npucfg_ar_size  ), 
    .cfg_axi_arburst (npucfg_ar_burst ), 
    .cfg_axi_arlock  (npucfg_ar_lock  ), 
    .cfg_axi_arcache (npucfg_ar_cache ), 
    .cfg_axi_arqos   (npucfg_ar_qos   ), 
    .cfg_axi_rready  (npucfg_r_ready  ), 
    .cfg_axi_rvalid  (npucfg_r_valid  ), 
    .cfg_axi_rresp   (npucfg_r_resp   ), 
    .cfg_axi_rdata   (npucfg_r_data   ), 
    .cfg_axi_rlast   (npucfg_r_last   ), 
    .cfg_axi_rid     (npucfg_r_id     ), 
    .cfg_axi_ruser   (npucfg_r_user   ), 
    .cfg_axi_awready (npucfg_aw_ready ), 
    .cfg_axi_awvalid (npucfg_aw_valid ), 
    .cfg_axi_awaddr  (npucfg_aw_addr  ), 
    .cfg_axi_awprot  (npucfg_aw_prot  ), 
    .cfg_axi_awid    (npucfg_aw_id    ), 
    .cfg_axi_awuser  (npucfg_aw_user  ), 
    .cfg_axi_awlen   (npucfg_aw_len   ), 
    .cfg_axi_awsize  (npucfg_aw_size  ), 
    .cfg_axi_awburst (npucfg_aw_burst ), 
    .cfg_axi_awlock  (npucfg_aw_lock  ), 
    .cfg_axi_awcache (npucfg_aw_cache ), 
    .cfg_axi_awqos   (npucfg_aw_qos   ), 
    .cfg_axi_wready  (npucfg_w_ready  ), 
    .cfg_axi_wvalid  (npucfg_w_valid  ), 
    .cfg_axi_wdata   (npucfg_w_data   ), 
    .cfg_axi_wstrb   (npucfg_w_strb   ), 
    .cfg_axi_wlast   (npucfg_w_last   ), 
    .cfg_axi_wuser   (npucfg_w_user   ), 
    .cfg_axi_bready  (npucfg_b_ready  ), 
    .cfg_axi_bvalid  (npucfg_b_valid  ), 
    .cfg_axi_bresp   (npucfg_b_resp   ), 
    .cfg_axi_bid     (npucfg_b_id     ), 
    .cfg_axi_buser   (npucfg_b_user   ),
    
    .axi_arready (npu_ar_ready ), 
    .axi_arvalid (npu_ar_valid ), 
    .axi_araddr  (npu_ar_addr  ), 
    .axi_arprot  (npu_ar_prot  ), 
    .axi_arid    (npu_ar_id    ), 
    .axi_aruser  (npu_ar_user  ), 
    .axi_arlen   (npu_ar_len   ), 
    .axi_arsize  (npu_ar_size  ), 
    .axi_arburst (npu_ar_burst ), 
    .axi_arlock  (npu_ar_lock  ), 
    .axi_arcache (npu_ar_cache ), 
    .axi_arqos   (npu_ar_qos   ), 
    .axi_rready  (npu_r_ready  ), 
    .axi_rvalid  (npu_r_valid  ), 
    .axi_rresp   (npu_r_resp   ), 
    .axi_rdata   (npu_r_data   ), 
    .axi_rlast   (npu_r_last   ), 
    .axi_rid     (npu_r_id     ), 
    .axi_ruser   (npu_r_user   ), 
    .axi_awready (npu_aw_ready ), 
    .axi_awvalid (npu_aw_valid ), 
    .axi_awaddr  (npu_aw_addr  ), 
    .axi_awprot  (npu_aw_prot  ), 
    .axi_awid    (npu_aw_id    ), 
    .axi_awuser  (npu_aw_user  ), 
    .axi_awlen   (npu_aw_len   ), 
    .axi_awsize  (npu_aw_size  ), 
    .axi_awburst (npu_aw_burst ), 
    .axi_awlock  (npu_aw_lock  ), 
    .axi_awcache (npu_aw_cache ), 
    .axi_awqos   (npu_aw_qos   ), 
    .axi_wready  (npu_w_ready  ), 
    .axi_wvalid  (npu_w_valid  ), 
    .axi_wdata   (npu_w_data   ), 
    .axi_wstrb   (npu_w_strb   ), 
    .axi_wlast   (npu_w_last   ), 
    .axi_wuser   (npu_w_user   ), 
    .axi_bready  (npu_b_ready  ), 
    .axi_bvalid  (npu_b_valid  ), 
    .axi_bresp   (npu_b_resp   ), 
    .axi_bid     (npu_b_id     ), 
    .axi_buser   (npu_b_user   )
);


Debug #(
  .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
  .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
  .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
  .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)DEBUG(
    .clk   (clk  ),
    .rst_n (rst_n),
    .cfg_axi_arready (debugcfg_ar_ready ), 
    .cfg_axi_arvalid (debugcfg_ar_valid ), 
    .cfg_axi_araddr  (debugcfg_ar_addr  ), 
    .cfg_axi_arprot  (debugcfg_ar_prot  ), 
    .cfg_axi_arid    (debugcfg_ar_id    ), 
    .cfg_axi_aruser  (debugcfg_ar_user  ), 
    .cfg_axi_arlen   (debugcfg_ar_len   ), 
    .cfg_axi_arsize  (debugcfg_ar_size  ), 
    .cfg_axi_arburst (debugcfg_ar_burst ), 
    .cfg_axi_arlock  (debugcfg_ar_lock  ), 
    .cfg_axi_arcache (debugcfg_ar_cache ), 
    .cfg_axi_arqos   (debugcfg_ar_qos   ), 
    .cfg_axi_rready  (debugcfg_r_ready  ), 
    .cfg_axi_rvalid  (debugcfg_r_valid  ), 
    .cfg_axi_rresp   (debugcfg_r_resp   ), 
    .cfg_axi_rdata   (debugcfg_r_data   ), 
    .cfg_axi_rlast   (debugcfg_r_last   ), 
    .cfg_axi_rid     (debugcfg_r_id     ), 
    .cfg_axi_ruser   (debugcfg_r_user   ), 
    .cfg_axi_awready (debugcfg_aw_ready ), 
    .cfg_axi_awvalid (debugcfg_aw_valid ), 
    .cfg_axi_awaddr  (debugcfg_aw_addr  ), 
    .cfg_axi_awprot  (debugcfg_aw_prot  ), 
    .cfg_axi_awid    (debugcfg_aw_id    ), 
    .cfg_axi_awuser  (debugcfg_aw_user  ), 
    .cfg_axi_awlen   (debugcfg_aw_len   ), 
    .cfg_axi_awsize  (debugcfg_aw_size  ), 
    .cfg_axi_awburst (debugcfg_aw_burst ), 
    .cfg_axi_awlock  (debugcfg_aw_lock  ), 
    .cfg_axi_awcache (debugcfg_aw_cache ), 
    .cfg_axi_awqos   (debugcfg_aw_qos   ), 
    .cfg_axi_wready  (debugcfg_w_ready  ), 
    .cfg_axi_wvalid  (debugcfg_w_valid  ), 
    .cfg_axi_wdata   (debugcfg_w_data   ), 
    .cfg_axi_wstrb   (debugcfg_w_strb   ), 
    .cfg_axi_wlast   (debugcfg_w_last   ), 
    .cfg_axi_wuser   (debugcfg_w_user   ), 
    .cfg_axi_bready  (debugcfg_b_ready  ), 
    .cfg_axi_bvalid  (debugcfg_b_valid  ), 
    .cfg_axi_bresp   (debugcfg_b_resp   ), 
    .cfg_axi_bid     (debugcfg_b_id     ), 
    .cfg_axi_buser   (debugcfg_b_user   ),
    
    .axi_arready (debug_ar_ready ), 
    .axi_arvalid (debug_ar_valid ), 
    .axi_araddr  (debug_ar_addr  ), 
    .axi_arprot  (debug_ar_prot  ), 
    .axi_arid    (debug_ar_id    ), 
    .axi_aruser  (debug_ar_user  ), 
    .axi_arlen   (debug_ar_len   ), 
    .axi_arsize  (debug_ar_size  ), 
    .axi_arburst (debug_ar_burst ), 
    .axi_arlock  (debug_ar_lock  ), 
    .axi_arcache (debug_ar_cache ), 
    .axi_arqos   (debug_ar_qos   ), 
    .axi_rready  (debug_r_ready  ), 
    .axi_rvalid  (debug_r_valid  ), 
    .axi_rresp   (debug_r_resp   ), 
    .axi_rdata   (debug_r_data   ), 
    .axi_rlast   (debug_r_last   ), 
    .axi_rid     (debug_r_id     ), 
    .axi_ruser   (debug_r_user   ), 
    .axi_awready (debug_aw_ready ), 
    .axi_awvalid (debug_aw_valid ), 
    .axi_awaddr  (debug_aw_addr  ), 
    .axi_awprot  (debug_aw_prot  ), 
    .axi_awid    (debug_aw_id    ), 
    .axi_awuser  (debug_aw_user  ), 
    .axi_awlen   (debug_aw_len   ), 
    .axi_awsize  (debug_aw_size  ), 
    .axi_awburst (debug_aw_burst ), 
    .axi_awlock  (debug_aw_lock  ), 
    .axi_awcache (debug_aw_cache ), 
    .axi_awqos   (debug_aw_qos   ), 
    .axi_wready  (debug_w_ready  ), 
    .axi_wvalid  (debug_w_valid  ), 
    .axi_wdata   (debug_w_data   ), 
    .axi_wstrb   (debug_w_strb   ), 
    .axi_wlast   (debug_w_last   ), 
    .axi_wuser   (debug_w_user   ), 
    .axi_bready  (debug_b_ready  ), 
    .axi_bvalid  (debug_b_valid  ), 
    .axi_bresp   (debug_b_resp   ), 
    .axi_bid     (debug_b_id     ), 
    .axi_buser   (debug_b_user   ),

    .jtag_TCK (jtag_TCK),
    .jtag_TMS (jtag_TMS),
    .jtag_TDI (jtag_TDI),
    .jtag_TDO (jtag_TDO),

    .halt_req_o  (),
    .reset_req_o ()
);


axi_interconnect_wrap_3x9 #
(
    .DATA_WIDTH(`AXI_DATA_WIDTH),
    .ADDR_WIDTH(`AXI_ADDR_WIDTH),
    .ID_WIDTH  (`AXI_ID_WIDTH  ),

    .M00_BASE_ADDR (`TIMER_BASE_ADDR),
    .M00_ADDR_WIDTH(`TIMER_RANGE    ),
    .M00_CONNECT_READ (3'b111),
    .M00_CONNECT_WRITE(3'b111),
    .M00_SECURE(1'b0),

    .M01_BASE_ADDR (`PLIC_BASE_ADDR ),
    .M01_ADDR_WIDTH(`PLIC_RANGE     ),
    .M01_CONNECT_READ (3'b111),
    .M01_CONNECT_WRITE(3'b111),
    .M01_SECURE(1'b0),

    .M02_BASE_ADDR (`UART_BASE_ADDR ),
    .M02_ADDR_WIDTH(`UART_RANGE     ),
    .M02_CONNECT_READ (3'b111),
    .M02_CONNECT_WRITE(3'b111),
    .M02_SECURE(1'b0),

    .M03_BASE_ADDR (`GPIO_BASE_ADDR ),
    .M03_ADDR_WIDTH(`GPIO_RANGE     ),
    .M03_CONNECT_READ (3'b111),
    .M03_CONNECT_WRITE(3'b111),
    .M03_SECURE(1'b0),

    .M04_BASE_ADDR (`SPI_BASE_ADDR ),
    .M04_ADDR_WIDTH(`SPI_RANGE     ),
    .M04_CONNECT_READ (3'b111),
    .M04_CONNECT_WRITE(3'b111),
    .M04_SECURE(1'b0),

    .M05_BASE_ADDR (`Debug_BASE_ADDR ),
    .M05_ADDR_WIDTH(`Debug_RANGE     ),
    .M05_CONNECT_READ (3'b111),
    .M05_CONNECT_WRITE(3'b111),
    .M05_SECURE(1'b0),

    .M06_BASE_ADDR (`ROM_BASE_ADDR ),
    .M06_ADDR_WIDTH(`ROM_RANGE     ),
    .M06_CONNECT_READ (3'b111),
    .M06_CONNECT_WRITE(3'b111),
    .M06_SECURE(1'b0),

    .M07_BASE_ADDR (`NPU_BASE_ADDR ),
    .M07_ADDR_WIDTH(`NPU_RANGE     ),
    .M07_CONNECT_READ (3'b111),
    .M07_CONNECT_WRITE(3'b111),
    .M07_SECURE(1'b0),

    .M08_BASE_ADDR (`DDR_BASE_ADDR ),
    .M08_ADDR_WIDTH(`DDR_RANGE     ),
    .M08_CONNECT_READ (3'b111),
    .M08_CONNECT_WRITE(3'b111),
    .M08_SECURE(1'b0)
) AXI_INTETCONNECT_3X9
(
    .clk (clk   ),
    .rst (~rst_n),
    /*
     * AXI slave interface
     */
    .s00_axi_arready (cpu_ar_ready ), 
    .s00_axi_arvalid (cpu_ar_valid ), 
    .s00_axi_araddr  (cpu_ar_addr  ), 
    .s00_axi_arprot  (cpu_ar_prot  ), 
    .s00_axi_arid    (cpu_ar_id    ), 
    .s00_axi_aruser  (cpu_ar_user  ), 
    .s00_axi_arlen   (cpu_ar_len   ), 
    .s00_axi_arsize  (cpu_ar_size  ), 
    .s00_axi_arburst (cpu_ar_burst ), 
    .s00_axi_arlock  (cpu_ar_lock  ), 
    .s00_axi_arcache (cpu_ar_cache ), 
    .s00_axi_arqos   (cpu_ar_qos   ), 
    .s00_axi_rready  (cpu_r_ready  ), 
    .s00_axi_rvalid  (cpu_r_valid  ), 
    .s00_axi_rresp   (cpu_r_resp   ), 
    .s00_axi_rdata   (cpu_r_data   ), 
    .s00_axi_rlast   (cpu_r_last   ), 
    .s00_axi_rid     (cpu_r_id     ), 
    .s00_axi_ruser   (cpu_r_user   ), 
    .s00_axi_awready (cpu_aw_ready ), 
    .s00_axi_awvalid (cpu_aw_valid ), 
    .s00_axi_awaddr  (cpu_aw_addr  ), 
    .s00_axi_awprot  (cpu_aw_prot  ), 
    .s00_axi_awid    (cpu_aw_id    ), 
    .s00_axi_awuser  (cpu_aw_user  ), 
    .s00_axi_awlen   (cpu_aw_len   ), 
    .s00_axi_awsize  (cpu_aw_size  ), 
    .s00_axi_awburst (cpu_aw_burst ), 
    .s00_axi_awlock  (cpu_aw_lock  ), 
    .s00_axi_awcache (cpu_aw_cache ), 
    .s00_axi_awqos   (cpu_aw_qos   ), 
    .s00_axi_wready  (cpu_w_ready  ), 
    .s00_axi_wvalid  (cpu_w_valid  ), 
    .s00_axi_wdata   (cpu_w_data   ), 
    .s00_axi_wstrb   (cpu_w_strb   ), 
    .s00_axi_wlast   (cpu_w_last   ), 
    .s00_axi_wuser   (cpu_w_user   ), 
    .s00_axi_bready  (cpu_b_ready  ), 
    .s00_axi_bvalid  (cpu_b_valid  ), 
    .s00_axi_bresp   (cpu_b_resp   ), 
    .s00_axi_bid     (cpu_b_id     ), 
    .s00_axi_buser   (cpu_b_user   ), 

    .s01_axi_arready (npu_ar_ready ), 
    .s01_axi_arvalid (npu_ar_valid ), 
    .s01_axi_araddr  (npu_ar_addr  ), 
    .s01_axi_arprot  (npu_ar_prot  ), 
    .s01_axi_arid    (npu_ar_id    ), 
    .s01_axi_aruser  (npu_ar_user  ), 
    .s01_axi_arlen   (npu_ar_len   ), 
    .s01_axi_arsize  (npu_ar_size  ), 
    .s01_axi_arburst (npu_ar_burst ), 
    .s01_axi_arlock  (npu_ar_lock  ), 
    .s01_axi_arcache (npu_ar_cache ), 
    .s01_axi_arqos   (npu_ar_qos   ), 
    .s01_axi_rready  (npu_r_ready  ), 
    .s01_axi_rvalid  (npu_r_valid  ), 
    .s01_axi_rresp   (npu_r_resp   ), 
    .s01_axi_rdata   (npu_r_data   ), 
    .s01_axi_rlast   (npu_r_last   ), 
    .s01_axi_rid     (npu_r_id     ), 
    .s01_axi_ruser   (npu_r_user   ), 
    .s01_axi_awready (npu_aw_ready ), 
    .s01_axi_awvalid (npu_aw_valid ), 
    .s01_axi_awaddr  (npu_aw_addr  ), 
    .s01_axi_awprot  (npu_aw_prot  ), 
    .s01_axi_awid    (npu_aw_id    ), 
    .s01_axi_awuser  (npu_aw_user  ), 
    .s01_axi_awlen   (npu_aw_len   ), 
    .s01_axi_awsize  (npu_aw_size  ), 
    .s01_axi_awburst (npu_aw_burst ), 
    .s01_axi_awlock  (npu_aw_lock  ), 
    .s01_axi_awcache (npu_aw_cache ), 
    .s01_axi_awqos   (npu_aw_qos   ), 
    .s01_axi_wready  (npu_w_ready  ), 
    .s01_axi_wvalid  (npu_w_valid  ), 
    .s01_axi_wdata   (npu_w_data   ), 
    .s01_axi_wstrb   (npu_w_strb   ), 
    .s01_axi_wlast   (npu_w_last   ), 
    .s01_axi_wuser   (npu_w_user   ), 
    .s01_axi_bready  (npu_b_ready  ), 
    .s01_axi_bvalid  (npu_b_valid  ), 
    .s01_axi_bresp   (npu_b_resp   ), 
    .s01_axi_bid     (npu_b_id     ), 
    .s01_axi_buser   (npu_b_user   ),

    .s02_axi_arready (debug_ar_ready ), 
    .s02_axi_arvalid (debug_ar_valid ), 
    .s02_axi_araddr  (debug_ar_addr  ), 
    .s02_axi_arprot  (debug_ar_prot  ), 
    .s02_axi_arid    (debug_ar_id    ), 
    .s02_axi_aruser  (debug_ar_user  ), 
    .s02_axi_arlen   (debug_ar_len   ), 
    .s02_axi_arsize  (debug_ar_size  ), 
    .s02_axi_arburst (debug_ar_burst ), 
    .s02_axi_arlock  (debug_ar_lock  ), 
    .s02_axi_arcache (debug_ar_cache ), 
    .s02_axi_arqos   (debug_ar_qos   ), 
    .s02_axi_rready  (debug_r_ready  ), 
    .s02_axi_rvalid  (debug_r_valid  ), 
    .s02_axi_rresp   (debug_r_resp   ), 
    .s02_axi_rdata   (debug_r_data   ), 
    .s02_axi_rlast   (debug_r_last   ), 
    .s02_axi_rid     (debug_r_id     ), 
    .s02_axi_ruser   (debug_r_user   ), 
    .s02_axi_awready (debug_aw_ready ), 
    .s02_axi_awvalid (debug_aw_valid ), 
    .s02_axi_awaddr  (debug_aw_addr  ), 
    .s02_axi_awprot  (debug_aw_prot  ), 
    .s02_axi_awid    (debug_aw_id    ), 
    .s02_axi_awuser  (debug_aw_user  ), 
    .s02_axi_awlen   (debug_aw_len   ), 
    .s02_axi_awsize  (debug_aw_size  ), 
    .s02_axi_awburst (debug_aw_burst ), 
    .s02_axi_awlock  (debug_aw_lock  ), 
    .s02_axi_awcache (debug_aw_cache ), 
    .s02_axi_awqos   (debug_aw_qos   ), 
    .s02_axi_wready  (debug_w_ready  ), 
    .s02_axi_wvalid  (debug_w_valid  ), 
    .s02_axi_wdata   (debug_w_data   ), 
    .s02_axi_wstrb   (debug_w_strb   ), 
    .s02_axi_wlast   (debug_w_last   ), 
    .s02_axi_wuser   (debug_w_user   ), 
    .s02_axi_bready  (debug_b_ready  ), 
    .s02_axi_bvalid  (debug_b_valid  ), 
    .s02_axi_bresp   (debug_b_resp   ), 
    .s02_axi_bid     (debug_b_id     ), 
    .s02_axi_buser   (debug_b_user   ),
   
    .m00_axi_arready (timer_ar_ready ), 
    .m00_axi_arvalid (timer_ar_valid ), 
    .m00_axi_araddr  (timer_ar_addr  ), 
    .m00_axi_arprot  (timer_ar_prot  ), 
    .m00_axi_arid    (timer_ar_id    ), 
    .m00_axi_aruser  (timer_ar_user  ), 
    .m00_axi_arlen   (timer_ar_len   ), 
    .m00_axi_arsize  (timer_ar_size  ), 
    .m00_axi_arburst (timer_ar_burst ), 
    .m00_axi_arlock  (timer_ar_lock  ), 
    .m00_axi_arcache (timer_ar_cache ), 
    .m00_axi_arqos   (timer_ar_qos   ), 
    .m00_axi_rready  (timer_r_ready  ), 
    .m00_axi_rvalid  (timer_r_valid  ), 
    .m00_axi_rresp   (timer_r_resp   ), 
    .m00_axi_rdata   (timer_r_data   ), 
    .m00_axi_rlast   (timer_r_last   ), 
    .m00_axi_rid     (timer_r_id     ), 
    .m00_axi_ruser   (timer_r_user   ), 
    .m00_axi_awready (timer_aw_ready ), 
    .m00_axi_awvalid (timer_aw_valid ), 
    .m00_axi_awaddr  (timer_aw_addr  ), 
    .m00_axi_awprot  (timer_aw_prot  ), 
    .m00_axi_awid    (timer_aw_id    ), 
    .m00_axi_awuser  (timer_aw_user  ), 
    .m00_axi_awlen   (timer_aw_len   ), 
    .m00_axi_awsize  (timer_aw_size  ), 
    .m00_axi_awburst (timer_aw_burst ), 
    .m00_axi_awlock  (timer_aw_lock  ), 
    .m00_axi_awcache (timer_aw_cache ), 
    .m00_axi_awqos   (timer_aw_qos   ), 
    .m00_axi_wready  (timer_w_ready  ), 
    .m00_axi_wvalid  (timer_w_valid  ), 
    .m00_axi_wdata   (timer_w_data   ), 
    .m00_axi_wstrb   (timer_w_strb   ), 
    .m00_axi_wlast   (timer_w_last   ), 
    .m00_axi_wuser   (timer_w_user   ), 
    .m00_axi_bready  (timer_b_ready  ), 
    .m00_axi_bvalid  (timer_b_valid  ), 
    .m00_axi_bresp   (timer_b_resp   ), 
    .m00_axi_bid     (timer_b_id     ), 
    .m00_axi_buser   (timer_b_user   ),

    .m01_axi_arready (plic_ar_ready ), 
    .m01_axi_arvalid (plic_ar_valid ), 
    .m01_axi_araddr  (plic_ar_addr  ), 
    .m01_axi_arprot  (plic_ar_prot  ), 
    .m01_axi_arid    (plic_ar_id    ), 
    .m01_axi_aruser  (plic_ar_user  ), 
    .m01_axi_arlen   (plic_ar_len   ), 
    .m01_axi_arsize  (plic_ar_size  ), 
    .m01_axi_arburst (plic_ar_burst ), 
    .m01_axi_arlock  (plic_ar_lock  ), 
    .m01_axi_arcache (plic_ar_cache ), 
    .m01_axi_arqos   (plic_ar_qos   ), 
    .m01_axi_rready  (plic_r_ready  ), 
    .m01_axi_rvalid  (plic_r_valid  ), 
    .m01_axi_rresp   (plic_r_resp   ), 
    .m01_axi_rdata   (plic_r_data   ), 
    .m01_axi_rlast   (plic_r_last   ), 
    .m01_axi_rid     (plic_r_id     ), 
    .m01_axi_ruser   (plic_r_user   ), 
    .m01_axi_awready (plic_aw_ready ), 
    .m01_axi_awvalid (plic_aw_valid ), 
    .m01_axi_awaddr  (plic_aw_addr  ), 
    .m01_axi_awprot  (plic_aw_prot  ), 
    .m01_axi_awid    (plic_aw_id    ), 
    .m01_axi_awuser  (plic_aw_user  ), 
    .m01_axi_awlen   (plic_aw_len   ), 
    .m01_axi_awsize  (plic_aw_size  ), 
    .m01_axi_awburst (plic_aw_burst ), 
    .m01_axi_awlock  (plic_aw_lock  ), 
    .m01_axi_awcache (plic_aw_cache ), 
    .m01_axi_awqos   (plic_aw_qos   ), 
    .m01_axi_wready  (plic_w_ready  ), 
    .m01_axi_wvalid  (plic_w_valid  ), 
    .m01_axi_wdata   (plic_w_data   ), 
    .m01_axi_wstrb   (plic_w_strb   ), 
    .m01_axi_wlast   (plic_w_last   ), 
    .m01_axi_wuser   (plic_w_user   ), 
    .m01_axi_bready  (plic_b_ready  ), 
    .m01_axi_bvalid  (plic_b_valid  ), 
    .m01_axi_bresp   (plic_b_resp   ), 
    .m01_axi_bid     (plic_b_id     ), 
    .m01_axi_buser   (plic_b_user   ),

    .m02_axi_arready (uart_ar_ready ), 
    .m02_axi_arvalid (uart_ar_valid ), 
    .m02_axi_araddr  (uart_ar_addr  ), 
    .m02_axi_arprot  (uart_ar_prot  ), 
    .m02_axi_arid    (uart_ar_id    ), 
    .m02_axi_aruser  (uart_ar_user  ), 
    .m02_axi_arlen   (uart_ar_len   ), 
    .m02_axi_arsize  (uart_ar_size  ), 
    .m02_axi_arburst (uart_ar_burst ), 
    .m02_axi_arlock  (uart_ar_lock  ), 
    .m02_axi_arcache (uart_ar_cache ), 
    .m02_axi_arqos   (uart_ar_qos   ), 
    .m02_axi_rready  (uart_r_ready  ), 
    .m02_axi_rvalid  (uart_r_valid  ), 
    .m02_axi_rresp   (uart_r_resp   ), 
    .m02_axi_rdata   (uart_r_data   ), 
    .m02_axi_rlast   (uart_r_last   ), 
    .m02_axi_rid     (uart_r_id     ), 
    .m02_axi_ruser   (uart_r_user   ), 
    .m02_axi_awready (uart_aw_ready ), 
    .m02_axi_awvalid (uart_aw_valid ), 
    .m02_axi_awaddr  (uart_aw_addr  ), 
    .m02_axi_awprot  (uart_aw_prot  ), 
    .m02_axi_awid    (uart_aw_id    ), 
    .m02_axi_awuser  (uart_aw_user  ), 
    .m02_axi_awlen   (uart_aw_len   ), 
    .m02_axi_awsize  (uart_aw_size  ), 
    .m02_axi_awburst (uart_aw_burst ), 
    .m02_axi_awlock  (uart_aw_lock  ), 
    .m02_axi_awcache (uart_aw_cache ), 
    .m02_axi_awqos   (uart_aw_qos   ), 
    .m02_axi_wready  (uart_w_ready  ), 
    .m02_axi_wvalid  (uart_w_valid  ), 
    .m02_axi_wdata   (uart_w_data   ), 
    .m02_axi_wstrb   (uart_w_strb   ), 
    .m02_axi_wlast   (uart_w_last   ), 
    .m02_axi_wuser   (uart_w_user   ), 
    .m02_axi_bready  (uart_b_ready  ), 
    .m02_axi_bvalid  (uart_b_valid  ), 
    .m02_axi_bresp   (uart_b_resp   ), 
    .m02_axi_bid     (uart_b_id     ), 
    .m02_axi_buser   (uart_b_user   ),

    .m03_axi_arready (gpio_ar_ready ), 
    .m03_axi_arvalid (gpio_ar_valid ), 
    .m03_axi_araddr  (gpio_ar_addr  ), 
    .m03_axi_arprot  (gpio_ar_prot  ), 
    .m03_axi_arid    (gpio_ar_id    ), 
    .m03_axi_aruser  (gpio_ar_user  ), 
    .m03_axi_arlen   (gpio_ar_len   ), 
    .m03_axi_arsize  (gpio_ar_size  ), 
    .m03_axi_arburst (gpio_ar_burst ), 
    .m03_axi_arlock  (gpio_ar_lock  ), 
    .m03_axi_arcache (gpio_ar_cache ), 
    .m03_axi_arqos   (gpio_ar_qos   ), 
    .m03_axi_rready  (gpio_r_ready  ), 
    .m03_axi_rvalid  (gpio_r_valid  ), 
    .m03_axi_rresp   (gpio_r_resp   ), 
    .m03_axi_rdata   (gpio_r_data   ), 
    .m03_axi_rlast   (gpio_r_last   ), 
    .m03_axi_rid     (gpio_r_id     ), 
    .m03_axi_ruser   (gpio_r_user   ), 
    .m03_axi_awready (gpio_aw_ready ), 
    .m03_axi_awvalid (gpio_aw_valid ), 
    .m03_axi_awaddr  (gpio_aw_addr  ), 
    .m03_axi_awprot  (gpio_aw_prot  ), 
    .m03_axi_awid    (gpio_aw_id    ), 
    .m03_axi_awuser  (gpio_aw_user  ), 
    .m03_axi_awlen   (gpio_aw_len   ), 
    .m03_axi_awsize  (gpio_aw_size  ), 
    .m03_axi_awburst (gpio_aw_burst ), 
    .m03_axi_awlock  (gpio_aw_lock  ), 
    .m03_axi_awcache (gpio_aw_cache ), 
    .m03_axi_awqos   (gpio_aw_qos   ), 
    .m03_axi_wready  (gpio_w_ready  ), 
    .m03_axi_wvalid  (gpio_w_valid  ), 
    .m03_axi_wdata   (gpio_w_data   ), 
    .m03_axi_wstrb   (gpio_w_strb   ), 
    .m03_axi_wlast   (gpio_w_last   ), 
    .m03_axi_wuser   (gpio_w_user   ), 
    .m03_axi_bready  (gpio_b_ready  ), 
    .m03_axi_bvalid  (gpio_b_valid  ), 
    .m03_axi_bresp   (gpio_b_resp   ), 
    .m03_axi_bid     (gpio_b_id     ), 
    .m03_axi_buser   (gpio_b_user   ),

    .m04_axi_arready (spi_ar_ready ), 
    .m04_axi_arvalid (spi_ar_valid ), 
    .m04_axi_araddr  (spi_ar_addr  ), 
    .m04_axi_arprot  (spi_ar_prot  ), 
    .m04_axi_arid    (spi_ar_id    ), 
    .m04_axi_aruser  (spi_ar_user  ), 
    .m04_axi_arlen   (spi_ar_len   ), 
    .m04_axi_arsize  (spi_ar_size  ), 
    .m04_axi_arburst (spi_ar_burst ), 
    .m04_axi_arlock  (spi_ar_lock  ), 
    .m04_axi_arcache (spi_ar_cache ), 
    .m04_axi_arqos   (spi_ar_qos   ), 
    .m04_axi_rready  (spi_r_ready  ), 
    .m04_axi_rvalid  (spi_r_valid  ), 
    .m04_axi_rresp   (spi_r_resp   ), 
    .m04_axi_rdata   (spi_r_data   ), 
    .m04_axi_rlast   (spi_r_last   ), 
    .m04_axi_rid     (spi_r_id     ), 
    .m04_axi_ruser   (spi_r_user   ), 
    .m04_axi_awready (spi_aw_ready ), 
    .m04_axi_awvalid (spi_aw_valid ), 
    .m04_axi_awaddr  (spi_aw_addr  ), 
    .m04_axi_awprot  (spi_aw_prot  ), 
    .m04_axi_awid    (spi_aw_id    ), 
    .m04_axi_awuser  (spi_aw_user  ), 
    .m04_axi_awlen   (spi_aw_len   ), 
    .m04_axi_awsize  (spi_aw_size  ), 
    .m04_axi_awburst (spi_aw_burst ), 
    .m04_axi_awlock  (spi_aw_lock  ), 
    .m04_axi_awcache (spi_aw_cache ), 
    .m04_axi_awqos   (spi_aw_qos   ), 
    .m04_axi_wready  (spi_w_ready  ), 
    .m04_axi_wvalid  (spi_w_valid  ), 
    .m04_axi_wdata   (spi_w_data   ), 
    .m04_axi_wstrb   (spi_w_strb   ), 
    .m04_axi_wlast   (spi_w_last   ), 
    .m04_axi_wuser   (spi_w_user   ), 
    .m04_axi_bready  (spi_b_ready  ), 
    .m04_axi_bvalid  (spi_b_valid  ), 
    .m04_axi_bresp   (spi_b_resp   ), 
    .m04_axi_bid     (spi_b_id     ), 
    .m04_axi_buser   (spi_b_user   ),

    .m05_axi_arready (debugcfg_ar_ready ), 
    .m05_axi_arvalid (debugcfg_ar_valid ), 
    .m05_axi_araddr  (debugcfg_ar_addr  ), 
    .m05_axi_arprot  (debugcfg_ar_prot  ), 
    .m05_axi_arid    (debugcfg_ar_id    ), 
    .m05_axi_aruser  (debugcfg_ar_user  ), 
    .m05_axi_arlen   (debugcfg_ar_len   ), 
    .m05_axi_arsize  (debugcfg_ar_size  ), 
    .m05_axi_arburst (debugcfg_ar_burst ), 
    .m05_axi_arlock  (debugcfg_ar_lock  ), 
    .m05_axi_arcache (debugcfg_ar_cache ), 
    .m05_axi_arqos   (debugcfg_ar_qos   ), 
    .m05_axi_rready  (debugcfg_r_ready  ), 
    .m05_axi_rvalid  (debugcfg_r_valid  ), 
    .m05_axi_rresp   (debugcfg_r_resp   ), 
    .m05_axi_rdata   (debugcfg_r_data   ), 
    .m05_axi_rlast   (debugcfg_r_last   ), 
    .m05_axi_rid     (debugcfg_r_id     ), 
    .m05_axi_ruser   (debugcfg_r_user   ), 
    .m05_axi_awready (debugcfg_aw_ready ), 
    .m05_axi_awvalid (debugcfg_aw_valid ), 
    .m05_axi_awaddr  (debugcfg_aw_addr  ), 
    .m05_axi_awprot  (debugcfg_aw_prot  ), 
    .m05_axi_awid    (debugcfg_aw_id    ), 
    .m05_axi_awuser  (debugcfg_aw_user  ), 
    .m05_axi_awlen   (debugcfg_aw_len   ), 
    .m05_axi_awsize  (debugcfg_aw_size  ), 
    .m05_axi_awburst (debugcfg_aw_burst ), 
    .m05_axi_awlock  (debugcfg_aw_lock  ), 
    .m05_axi_awcache (debugcfg_aw_cache ), 
    .m05_axi_awqos   (debugcfg_aw_qos   ), 
    .m05_axi_wready  (debugcfg_w_ready  ), 
    .m05_axi_wvalid  (debugcfg_w_valid  ), 
    .m05_axi_wdata   (debugcfg_w_data   ), 
    .m05_axi_wstrb   (debugcfg_w_strb   ), 
    .m05_axi_wlast   (debugcfg_w_last   ), 
    .m05_axi_wuser   (debugcfg_w_user   ), 
    .m05_axi_bready  (debugcfg_b_ready  ), 
    .m05_axi_bvalid  (debugcfg_b_valid  ), 
    .m05_axi_bresp   (debugcfg_b_resp   ), 
    .m05_axi_bid     (debugcfg_b_id     ), 
    .m05_axi_buser   (debugcfg_b_user   ),

    .m06_axi_arready (bootrom_ar_ready ), 
    .m06_axi_arvalid (bootrom_ar_valid ), 
    .m06_axi_araddr  (bootrom_ar_addr  ), 
    .m06_axi_arprot  (bootrom_ar_prot  ), 
    .m06_axi_arid    (bootrom_ar_id    ), 
    .m06_axi_aruser  (bootrom_ar_user  ), 
    .m06_axi_arlen   (bootrom_ar_len   ), 
    .m06_axi_arsize  (bootrom_ar_size  ), 
    .m06_axi_arburst (bootrom_ar_burst ), 
    .m06_axi_arlock  (bootrom_ar_lock  ), 
    .m06_axi_arcache (bootrom_ar_cache ), 
    .m06_axi_arqos   (bootrom_ar_qos   ), 
    .m06_axi_rready  (bootrom_r_ready  ), 
    .m06_axi_rvalid  (bootrom_r_valid  ), 
    .m06_axi_rresp   (bootrom_r_resp   ), 
    .m06_axi_rdata   (bootrom_r_data   ), 
    .m06_axi_rlast   (bootrom_r_last   ), 
    .m06_axi_rid     (bootrom_r_id     ), 
    .m06_axi_ruser   (bootrom_r_user   ), 
    .m06_axi_awready (bootrom_aw_ready ), 
    .m06_axi_awvalid (bootrom_aw_valid ), 
    .m06_axi_awaddr  (bootrom_aw_addr  ), 
    .m06_axi_awprot  (bootrom_aw_prot  ), 
    .m06_axi_awid    (bootrom_aw_id    ), 
    .m06_axi_awuser  (bootrom_aw_user  ), 
    .m06_axi_awlen   (bootrom_aw_len   ), 
    .m06_axi_awsize  (bootrom_aw_size  ), 
    .m06_axi_awburst (bootrom_aw_burst ), 
    .m06_axi_awlock  (bootrom_aw_lock  ), 
    .m06_axi_awcache (bootrom_aw_cache ), 
    .m06_axi_awqos   (bootrom_aw_qos   ), 
    .m06_axi_wready  (bootrom_w_ready  ), 
    .m06_axi_wvalid  (bootrom_w_valid  ), 
    .m06_axi_wdata   (bootrom_w_data   ), 
    .m06_axi_wstrb   (bootrom_w_strb   ), 
    .m06_axi_wlast   (bootrom_w_last   ), 
    .m06_axi_wuser   (bootrom_w_user   ), 
    .m06_axi_bready  (bootrom_b_ready  ), 
    .m06_axi_bvalid  (bootrom_b_valid  ), 
    .m06_axi_bresp   (bootrom_b_resp   ), 
    .m06_axi_bid     (bootrom_b_id     ), 
    .m06_axi_buser   (bootrom_b_user   ),

    .m07_axi_arready (npucfg_ar_ready ), 
    .m07_axi_arvalid (npucfg_ar_valid ), 
    .m07_axi_araddr  (npucfg_ar_addr  ), 
    .m07_axi_arprot  (npucfg_ar_prot  ), 
    .m07_axi_arid    (npucfg_ar_id    ), 
    .m07_axi_aruser  (npucfg_ar_user  ), 
    .m07_axi_arlen   (npucfg_ar_len   ), 
    .m07_axi_arsize  (npucfg_ar_size  ), 
    .m07_axi_arburst (npucfg_ar_burst ), 
    .m07_axi_arlock  (npucfg_ar_lock  ), 
    .m07_axi_arcache (npucfg_ar_cache ), 
    .m07_axi_arqos   (npucfg_ar_qos   ), 
    .m07_axi_rready  (npucfg_r_ready  ), 
    .m07_axi_rvalid  (npucfg_r_valid  ), 
    .m07_axi_rresp   (npucfg_r_resp   ), 
    .m07_axi_rdata   (npucfg_r_data   ), 
    .m07_axi_rlast   (npucfg_r_last   ), 
    .m07_axi_rid     (npucfg_r_id     ), 
    .m07_axi_ruser   (npucfg_r_user   ), 
    .m07_axi_awready (npucfg_aw_ready ), 
    .m07_axi_awvalid (npucfg_aw_valid ), 
    .m07_axi_awaddr  (npucfg_aw_addr  ), 
    .m07_axi_awprot  (npucfg_aw_prot  ), 
    .m07_axi_awid    (npucfg_aw_id    ), 
    .m07_axi_awuser  (npucfg_aw_user  ), 
    .m07_axi_awlen   (npucfg_aw_len   ), 
    .m07_axi_awsize  (npucfg_aw_size  ), 
    .m07_axi_awburst (npucfg_aw_burst ), 
    .m07_axi_awlock  (npucfg_aw_lock  ), 
    .m07_axi_awcache (npucfg_aw_cache ), 
    .m07_axi_awqos   (npucfg_aw_qos   ), 
    .m07_axi_wready  (npucfg_w_ready  ), 
    .m07_axi_wvalid  (npucfg_w_valid  ), 
    .m07_axi_wdata   (npucfg_w_data   ), 
    .m07_axi_wstrb   (npucfg_w_strb   ), 
    .m07_axi_wlast   (npucfg_w_last   ), 
    .m07_axi_wuser   (npucfg_w_user   ), 
    .m07_axi_bready  (npucfg_b_ready  ), 
    .m07_axi_bvalid  (npucfg_b_valid  ), 
    .m07_axi_bresp   (npucfg_b_resp   ), 
    .m07_axi_bid     (npucfg_b_id     ), 
    .m07_axi_buser   (npucfg_b_user   ),

    .m08_axi_arready (ddr_ar_ready ), 
    .m08_axi_arvalid (ddr_ar_valid ), 
    .m08_axi_araddr  (ddr_ar_addr  ), 
    .m08_axi_arprot  (ddr_ar_prot  ), 
    .m08_axi_arid    (ddr_ar_id    ), 
    .m08_axi_aruser  (ddr_ar_user  ), 
    .m08_axi_arlen   (ddr_ar_len   ), 
    .m08_axi_arsize  (ddr_ar_size  ), 
    .m08_axi_arburst (ddr_ar_burst ), 
    .m08_axi_arlock  (ddr_ar_lock  ), 
    .m08_axi_arcache (ddr_ar_cache ), 
    .m08_axi_arqos   (ddr_ar_qos   ), 
    .m08_axi_rready  (ddr_r_ready  ), 
    .m08_axi_rvalid  (ddr_r_valid  ), 
    .m08_axi_rresp   (ddr_r_resp   ), 
    .m08_axi_rdata   (ddr_r_data   ), 
    .m08_axi_rlast   (ddr_r_last   ), 
    .m08_axi_rid     (ddr_r_id     ), 
    .m08_axi_ruser   (ddr_r_user   ), 
    .m08_axi_awready (ddr_aw_ready ), 
    .m08_axi_awvalid (ddr_aw_valid ), 
    .m08_axi_awaddr  (ddr_aw_addr  ), 
    .m08_axi_awprot  (ddr_aw_prot  ), 
    .m08_axi_awid    (ddr_aw_id    ), 
    .m08_axi_awuser  (ddr_aw_user  ), 
    .m08_axi_awlen   (ddr_aw_len   ), 
    .m08_axi_awsize  (ddr_aw_size  ), 
    .m08_axi_awburst (ddr_aw_burst ), 
    .m08_axi_awlock  (ddr_aw_lock  ), 
    .m08_axi_awcache (ddr_aw_cache ), 
    .m08_axi_awqos   (ddr_aw_qos   ), 
    .m08_axi_wready  (ddr_w_ready  ), 
    .m08_axi_wvalid  (ddr_w_valid  ), 
    .m08_axi_wdata   (ddr_w_data   ), 
    .m08_axi_wstrb   (ddr_w_strb   ), 
    .m08_axi_wlast   (ddr_w_last   ), 
    .m08_axi_wuser   (ddr_w_user   ), 
    .m08_axi_bready  (ddr_b_ready  ), 
    .m08_axi_bvalid  (ddr_b_valid  ), 
    .m08_axi_bresp   (ddr_b_resp   ), 
    .m08_axi_bid     (ddr_b_id     ), 
    .m08_axi_buser   (ddr_b_user   ),
    .m00_axi_awregion (),
    .m00_axi_arregion (),
    .m01_axi_awregion (),
    .m01_axi_arregion (),
    .m02_axi_awregion (),
    .m02_axi_arregion (),
    .m03_axi_awregion (),
    .m03_axi_arregion (),
    .m04_axi_awregion (),
    .m04_axi_arregion (),
    .m05_axi_awregion (),
    .m05_axi_arregion (),
    .m06_axi_awregion (),
    .m06_axi_arregion (),
    .m07_axi_awregion (),
    .m07_axi_arregion (),
    .m08_axi_awregion (),
    .m08_axi_arregion ()
);

// Timer 
axi_timer #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_TIMER(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (timer_ar_ready ), 
    .axi_arvalid (timer_ar_valid ), 
    .axi_araddr  (timer_ar_addr  ), 
    .axi_arprot  (timer_ar_prot  ), 
    .axi_arid    (timer_ar_id    ), 
    .axi_aruser  (timer_ar_user  ), 
    .axi_arlen   (timer_ar_len   ), 
    .axi_arsize  (timer_ar_size  ), 
    .axi_arburst (timer_ar_burst ), 
    .axi_arlock  (timer_ar_lock  ), 
    .axi_arcache (timer_ar_cache ), 
    .axi_arqos   (timer_ar_qos   ), 
    .axi_rready  (timer_r_ready  ), 
    .axi_rvalid  (timer_r_valid  ), 
    .axi_rresp   (timer_r_resp   ), 
    .axi_rdata   (timer_r_data   ), 
    .axi_rlast   (timer_r_last   ), 
    .axi_rid     (timer_r_id     ), 
    .axi_ruser   (timer_r_user   ), 
    .axi_awready (timer_aw_ready ), 
    .axi_awvalid (timer_aw_valid ), 
    .axi_awaddr  (timer_aw_addr  ), 
    .axi_awprot  (timer_aw_prot  ), 
    .axi_awid    (timer_aw_id    ), 
    .axi_awuser  (timer_aw_user  ), 
    .axi_awlen   (timer_aw_len   ), 
    .axi_awsize  (timer_aw_size  ), 
    .axi_awburst (timer_aw_burst ), 
    .axi_awlock  (timer_aw_lock  ), 
    .axi_awcache (timer_aw_cache ), 
    .axi_awqos   (timer_aw_qos   ), 
    .axi_wready  (timer_w_ready  ), 
    .axi_wvalid  (timer_w_valid  ), 
    .axi_wdata   (timer_w_data   ), 
    .axi_wstrb   (timer_w_strb   ), 
    .axi_wlast   (timer_w_last   ), 
    .axi_wuser   (timer_w_user   ), 
    .axi_bready  (timer_b_ready  ), 
    .axi_bvalid  (timer_b_valid  ), 
    .axi_bresp   (timer_b_resp   ), 
    .axi_bid     (timer_b_id     ), 
    .axi_buser   (timer_b_user   )
);


// PLIC 
axi_plic #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_PLIC(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (timer_ar_ready ), 
    .axi_arvalid (timer_ar_valid ), 
    .axi_araddr  (timer_ar_addr  ), 
    .axi_arprot  (timer_ar_prot  ), 
    .axi_arid    (timer_ar_id    ), 
    .axi_aruser  (timer_ar_user  ), 
    .axi_arlen   (timer_ar_len   ), 
    .axi_arsize  (timer_ar_size  ), 
    .axi_arburst (timer_ar_burst ), 
    .axi_arlock  (timer_ar_lock  ), 
    .axi_arcache (timer_ar_cache ), 
    .axi_arqos   (timer_ar_qos   ), 
    .axi_rready  (timer_r_ready  ), 
    .axi_rvalid  (timer_r_valid  ), 
    .axi_rresp   (timer_r_resp   ), 
    .axi_rdata   (timer_r_data   ), 
    .axi_rlast   (timer_r_last   ), 
    .axi_rid     (timer_r_id     ), 
    .axi_ruser   (timer_r_user   ), 
    .axi_awready (timer_aw_ready ), 
    .axi_awvalid (timer_aw_valid ), 
    .axi_awaddr  (timer_aw_addr  ), 
    .axi_awprot  (timer_aw_prot  ), 
    .axi_awid    (timer_aw_id    ), 
    .axi_awuser  (timer_aw_user  ), 
    .axi_awlen   (timer_aw_len   ), 
    .axi_awsize  (timer_aw_size  ), 
    .axi_awburst (timer_aw_burst ), 
    .axi_awlock  (timer_aw_lock  ), 
    .axi_awcache (timer_aw_cache ), 
    .axi_awqos   (timer_aw_qos   ), 
    .axi_wready  (timer_w_ready  ), 
    .axi_wvalid  (timer_w_valid  ), 
    .axi_wdata   (timer_w_data   ), 
    .axi_wstrb   (timer_w_strb   ), 
    .axi_wlast   (timer_w_last   ), 
    .axi_wuser   (timer_w_user   ), 
    .axi_bready  (timer_b_ready  ), 
    .axi_bvalid  (timer_b_valid  ), 
    .axi_bresp   (timer_b_resp   ), 
    .axi_bid     (timer_b_id     ), 
    .axi_buser   (timer_b_user   )
);

// UART 
axi_uart #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_UART(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (uart_ar_ready ), 
    .axi_arvalid (uart_ar_valid ), 
    .axi_araddr  (uart_ar_addr  ), 
    .axi_arprot  (uart_ar_prot  ), 
    .axi_arid    (uart_ar_id    ), 
    .axi_aruser  (uart_ar_user  ), 
    .axi_arlen   (uart_ar_len   ), 
    .axi_arsize  (uart_ar_size  ), 
    .axi_arburst (uart_ar_burst ), 
    .axi_arlock  (uart_ar_lock  ), 
    .axi_arcache (uart_ar_cache ), 
    .axi_arqos   (uart_ar_qos   ), 
    .axi_rready  (uart_r_ready  ), 
    .axi_rvalid  (uart_r_valid  ), 
    .axi_rresp   (uart_r_resp   ), 
    .axi_rdata   (uart_r_data   ), 
    .axi_rlast   (uart_r_last   ), 
    .axi_rid     (uart_r_id     ), 
    .axi_ruser   (uart_r_user   ), 
    .axi_awready (uart_aw_ready ), 
    .axi_awvalid (uart_aw_valid ), 
    .axi_awaddr  (uart_aw_addr  ), 
    .axi_awprot  (uart_aw_prot  ), 
    .axi_awid    (uart_aw_id    ), 
    .axi_awuser  (uart_aw_user  ), 
    .axi_awlen   (uart_aw_len   ), 
    .axi_awsize  (uart_aw_size  ), 
    .axi_awburst (uart_aw_burst ), 
    .axi_awlock  (uart_aw_lock  ), 
    .axi_awcache (uart_aw_cache ), 
    .axi_awqos   (uart_aw_qos   ), 
    .axi_wready  (uart_w_ready  ), 
    .axi_wvalid  (uart_w_valid  ), 
    .axi_wdata   (uart_w_data   ), 
    .axi_wstrb   (uart_w_strb   ), 
    .axi_wlast   (uart_w_last   ), 
    .axi_wuser   (uart_w_user   ), 
    .axi_bready  (uart_b_ready  ), 
    .axi_bvalid  (uart_b_valid  ), 
    .axi_bresp   (uart_b_resp   ), 
    .axi_bid     (uart_b_id     ), 
    .axi_buser   (uart_b_user   ),
    .rx          (uart_rx),
    .tx          (uart_tx)
);


// GPIO
axi_gpio #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_GPIO(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (gpio_ar_ready ), 
    .axi_arvalid (gpio_ar_valid ), 
    .axi_araddr  (gpio_ar_addr  ), 
    .axi_arprot  (gpio_ar_prot  ), 
    .axi_arid    (gpio_ar_id    ), 
    .axi_aruser  (gpio_ar_user  ), 
    .axi_arlen   (gpio_ar_len   ), 
    .axi_arsize  (gpio_ar_size  ), 
    .axi_arburst (gpio_ar_burst ), 
    .axi_arlock  (gpio_ar_lock  ), 
    .axi_arcache (gpio_ar_cache ), 
    .axi_arqos   (gpio_ar_qos   ), 
    .axi_rready  (gpio_r_ready  ), 
    .axi_rvalid  (gpio_r_valid  ), 
    .axi_rresp   (gpio_r_resp   ), 
    .axi_rdata   (gpio_r_data   ), 
    .axi_rlast   (gpio_r_last   ), 
    .axi_rid     (gpio_r_id     ), 
    .axi_ruser   (gpio_r_user   ), 
    .axi_awready (gpio_aw_ready ), 
    .axi_awvalid (gpio_aw_valid ), 
    .axi_awaddr  (gpio_aw_addr  ), 
    .axi_awprot  (gpio_aw_prot  ), 
    .axi_awid    (gpio_aw_id    ), 
    .axi_awuser  (gpio_aw_user  ), 
    .axi_awlen   (gpio_aw_len   ), 
    .axi_awsize  (gpio_aw_size  ), 
    .axi_awburst (gpio_aw_burst ), 
    .axi_awlock  (gpio_aw_lock  ), 
    .axi_awcache (gpio_aw_cache ), 
    .axi_awqos   (gpio_aw_qos   ), 
    .axi_wready  (gpio_w_ready  ), 
    .axi_wvalid  (gpio_w_valid  ), 
    .axi_wdata   (gpio_w_data   ), 
    .axi_wstrb   (gpio_w_strb   ), 
    .axi_wlast   (gpio_w_last   ), 
    .axi_wuser   (gpio_w_user   ), 
    .axi_bready  (gpio_b_ready  ), 
    .axi_bvalid  (gpio_b_valid  ), 
    .axi_bresp   (gpio_b_resp   ), 
    .axi_bid     (gpio_b_id     ), 
    .axi_buser   (gpio_b_user   ),
    .gpio_i      (gpio_i        ),
    .gpio_o      (gpio_o        ),
    .gpio_oe     (gpio_oe       ) 
);

// SPI
axi_spi #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_SPI(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (spi_ar_ready ), 
    .axi_arvalid (spi_ar_valid ), 
    .axi_araddr  (spi_ar_addr  ), 
    .axi_arprot  (spi_ar_prot  ), 
    .axi_arid    (spi_ar_id    ), 
    .axi_aruser  (spi_ar_user  ), 
    .axi_arlen   (spi_ar_len   ), 
    .axi_arsize  (spi_ar_size  ), 
    .axi_arburst (spi_ar_burst ), 
    .axi_arlock  (spi_ar_lock  ), 
    .axi_arcache (spi_ar_cache ), 
    .axi_arqos   (spi_ar_qos   ), 
    .axi_rready  (spi_r_ready  ), 
    .axi_rvalid  (spi_r_valid  ), 
    .axi_rresp   (spi_r_resp   ), 
    .axi_rdata   (spi_r_data   ), 
    .axi_rlast   (spi_r_last   ), 
    .axi_rid     (spi_r_id     ), 
    .axi_ruser   (spi_r_user   ), 
    .axi_awready (spi_aw_ready ), 
    .axi_awvalid (spi_aw_valid ), 
    .axi_awaddr  (spi_aw_addr  ), 
    .axi_awprot  (spi_aw_prot  ), 
    .axi_awid    (spi_aw_id    ), 
    .axi_awuser  (spi_aw_user  ), 
    .axi_awlen   (spi_aw_len   ), 
    .axi_awsize  (spi_aw_size  ), 
    .axi_awburst (spi_aw_burst ), 
    .axi_awlock  (spi_aw_lock  ), 
    .axi_awcache (spi_aw_cache ), 
    .axi_awqos   (spi_aw_qos   ), 
    .axi_wready  (spi_w_ready  ), 
    .axi_wvalid  (spi_w_valid  ), 
    .axi_wdata   (spi_w_data   ), 
    .axi_wstrb   (spi_w_strb   ), 
    .axi_wlast   (spi_w_last   ), 
    .axi_wuser   (spi_w_user   ), 
    .axi_bready  (spi_b_ready  ), 
    .axi_bvalid  (spi_b_valid  ), 
    .axi_bresp   (spi_b_resp   ), 
    .axi_bid     (spi_b_id     ), 
    .axi_buser   (spi_b_user   ),
    .spi_clk     (spi_clk ), 
    .spi_csn0    (spi_csn0), 
    .spi_csn1    (spi_csn1), 
    .spi_csn2    (spi_csn2), 
    .spi_csn3    (spi_csn3), 
    .spi_sdo0    (spi_sdo0), 
    .spi_sdo1    (spi_sdo1), 
    .spi_sdo2    (spi_sdo2), 
    .spi_sdo3    (spi_sdo3), 
    .spi_oe0     (spi_oe0 ), 
    .spi_oe1     (spi_oe1 ), 
    .spi_oe2     (spi_oe2 ), 
    .spi_oe3     (spi_oe3 ), 
    .spi_sdi0    (spi_sdi0), 
    .spi_sdi1    (spi_sdi1), 
    .spi_sdi2    (spi_sdi2), 
    .spi_sdi3    (spi_sdi3)
);

// BOOTROM
axi_bootrom #(
   .AXI_ID_WIDTH   (`AXI_ID_WIDTH   ),
   .AXI_ADDR_WIDTH (`AXI_ADDR_WIDTH ),
   .AXI_DATA_WIDTH (`AXI_DATA_WIDTH ),
   .AXI_USER_WIDTH (`AXI_USER_WIDTH )
)AXI_BOOTROM(
    .clk   (clk  ),
    .rst_n (rst_n),
    .axi_arready (bootrom_ar_ready ), 
    .axi_arvalid (bootrom_ar_valid ), 
    .axi_araddr  (bootrom_ar_addr  ), 
    .axi_arprot  (bootrom_ar_prot  ), 
    .axi_arid    (bootrom_ar_id    ), 
    .axi_aruser  (bootrom_ar_user  ), 
    .axi_arlen   (bootrom_ar_len   ), 
    .axi_arsize  (bootrom_ar_size  ), 
    .axi_arburst (bootrom_ar_burst ), 
    .axi_arlock  (bootrom_ar_lock  ), 
    .axi_arcache (bootrom_ar_cache ), 
    .axi_arqos   (bootrom_ar_qos   ), 
    .axi_rready  (bootrom_r_ready  ), 
    .axi_rvalid  (bootrom_r_valid  ), 
    .axi_rresp   (bootrom_r_resp   ), 
    .axi_rdata   (bootrom_r_data   ), 
    .axi_rlast   (bootrom_r_last   ), 
    .axi_rid     (bootrom_r_id     ), 
    .axi_ruser   (bootrom_r_user   ), 
    .axi_awready (bootrom_aw_ready ), 
    .axi_awvalid (bootrom_aw_valid ), 
    .axi_awaddr  (bootrom_aw_addr  ), 
    .axi_awprot  (bootrom_aw_prot  ), 
    .axi_awid    (bootrom_aw_id    ), 
    .axi_awuser  (bootrom_aw_user  ), 
    .axi_awlen   (bootrom_aw_len   ), 
    .axi_awsize  (bootrom_aw_size  ), 
    .axi_awburst (bootrom_aw_burst ), 
    .axi_awlock  (bootrom_aw_lock  ), 
    .axi_awcache (bootrom_aw_cache ), 
    .axi_awqos   (bootrom_aw_qos   ), 
    .axi_wready  (bootrom_w_ready  ), 
    .axi_wvalid  (bootrom_w_valid  ), 
    .axi_wdata   (bootrom_w_data   ), 
    .axi_wstrb   (bootrom_w_strb   ), 
    .axi_wlast   (bootrom_w_last   ), 
    .axi_wuser   (bootrom_w_user   ), 
    .axi_bready  (bootrom_b_ready  ), 
    .axi_bvalid  (bootrom_b_valid  ), 
    .axi_bresp   (bootrom_b_resp   ), 
    .axi_bid     (bootrom_b_id     ), 
    .axi_buser   (bootrom_b_user   )
);

// DDR
axi_ram AXI_DDR(
    .clk   (clk   ),
    .rst   (~rst_n),
    .s_axi_arready (ddr_ar_ready ), 
    .s_axi_arvalid (ddr_ar_valid ), 
    .s_axi_araddr  (ddr_ar_addr  ), 
    .s_axi_arprot  (ddr_ar_prot  ), 
    .s_axi_arid    (ddr_ar_id    ), 
    // .s_axi_aruser  (ddr_ar_user  ), 
    .s_axi_arlen   (ddr_ar_len   ), 
    .s_axi_arsize  (ddr_ar_size  ), 
    .s_axi_arburst (ddr_ar_burst ), 
    .s_axi_arlock  (ddr_ar_lock  ), 
    .s_axi_arcache (ddr_ar_cache ), 
    // .s_axi_arqos   (ddr_ar_qos   ), 
    .s_axi_rready  (ddr_r_ready  ), 
    .s_axi_rvalid  (ddr_r_valid  ), 
    .s_axi_rresp   (ddr_r_resp   ), 
    .s_axi_rdata   (ddr_r_data   ), 
    .s_axi_rlast   (ddr_r_last   ), 
    .s_axi_rid     (ddr_r_id     ), 
    // .s_axi_ruser   (ddr_r_user   ), 
    .s_axi_awready (ddr_aw_ready ), 
    .s_axi_awvalid (ddr_aw_valid ), 
    .s_axi_awaddr  (ddr_aw_addr  ), 
    .s_axi_awprot  (ddr_aw_prot  ), 
    .s_axi_awid    (ddr_aw_id    ), 
    // .s_axi_awuser  (ddr_aw_user  ), 
    .s_axi_awlen   (ddr_aw_len   ), 
    .s_axi_awsize  (ddr_aw_size  ), 
    .s_axi_awburst (ddr_aw_burst ), 
    .s_axi_awlock  (ddr_aw_lock  ), 
    .s_axi_awcache (ddr_aw_cache ), 
    // .s_axi_awqos   (ddr_aw_qos   ), 
    .s_axi_wready  (ddr_w_ready  ), 
    .s_axi_wvalid  (ddr_w_valid  ), 
    .s_axi_wdata   (ddr_w_data   ), 
    .s_axi_wstrb   (ddr_w_strb   ), 
    .s_axi_wlast   (ddr_w_last   ), 
    // .s_axi_wuser   (ddr_w_user   ), 
    .s_axi_bready  (ddr_b_ready  ), 
    .s_axi_bvalid  (ddr_b_valid  ), 
    .s_axi_bresp   (ddr_b_resp   ), 
    .s_axi_bid     (ddr_b_id     )
    // .s_axi_buser   (ddr_b_user   )
);


endmodule